Unit 2: Arithmetic Unit

Unit 2: Arithmetic Unit

Part A:

1. What is the purpose of guard bits used in floating point operations?
2. Give the booth’s recording and bit-pair recording of the number 1000111101000101.
3. Perform the division on the following 5-bit unsigned integer using non-restoring division: 10101/00101.
4. Give the IEEE standard double precision floating point format.
5. Draw the symbolic representation of the full adder and give the expression for the sum.
6. Why floating point number is more difficult to represent and process than integer?
7. Draw a full adder circuit and give the truth table.
8. Discuss the principle behind Booth’s multiplier.
9. What is ripple carry adder?

10. In conforming to the IEEE standard mention any four situations under which a processor sets exception flag.

Part B:

1. Explain in detail the principle of carry-look-ahead adder. Show how 16-bit CLAs can be constructed from 4-bit adders.
2. Explain the working of floating point adder/subtractor.
3. Multiply the following pair of signed 2’s complements nos. using bit-pair recoding of the multipliers: A = 010111, B = 101100.
4. Draw the diagram of a carry look ahead adder and explain the carry look ahead principle.
5. Explain the floating point Add/Subtract rules. With a detailed flowchart explain how floating point addition/subtraction is performed.
6. Give the block diagram of the hardware implementation of addition and subtraction of signed no and explain the operations with flowchart.
7. Explain the representations of floating point nos in detail.
8. Design a multiplier that multiplies two 4-bit nos.
9. Describe the algorithm for integer division with suitable example.
10. Describe the principle of operation of carry-look ahead adders.
11. Discuss the non-restoring division algorithm. Simulate the same for 23/5.
12. Discuss the concept of bit pair recoding.
Simulate the addition and subtraction operations (A + (OR) – B) on the operands: A = 0 10001 011011 , B = 1 01111 101010 with a five-bit signed excess-15 exponent and a six-bit normalized fractional mantissa.

COMPUTER ARCHITECTURE syllabus

COMPUTER ARCHITECTURE
UNIT: I BASIC STRUCTURE OF COMPUTERS
Functional Units T:3-7
Basic Operational Concepts T:7-9
Bus Structures T:9-10
Software Performance T:10-18
Memory Locations and Addresses T:33-36
Memory Operations T:36-37
Instruction & Instruction Sequencing T:37-47
Addressing Modes T:48-58
Assembly Language T:58-64
Basic I/O Operations T:64-68
Stacks and Queues T:68-72

UNIT: II ARITHMETIC UNIT

Addition & Subtraction of Signed NosT:368-371
Design of Fast Adders T:371-376
Multiplication of Positive Numbers T:376-379
Signed Operand Multiplication T:380-383
Fast Multiplication T:383-390
Integer Division T:390-393
Floating Point Nos. & Operations T:393-402

UNIT: III BASIC PROCESSING UNIT

Fundamental Concepts T:412-420
Execution of a Complete Inst. T:421-423
Multiple Bus Organization T:423-425
Hardwired Control T:425-429
Micro programmed Control T:429-445
Pipelining T:454
Basic Concepts T:454-461
Data Hazards T:461-465
Instruction Hazards T:465-476
Influence on Instruction Sets T:476-479
Data Path & Control ConsiderationT:479-481
Superscalar Operation T:481-486
Performance Considerations T:503-505

UNIT: IV I/O ORGANIZATION

Accessing I/O Devices T:204-207
Interrupts T:208-223
Direct Memory Access T:234-240
Buses T:240-247
Interface Circuits T:248-259
Standard I/O Interfaces T:259-261
PCI T:261-266
SCSI T:266-272
USB T:272-282

UNIT: V MEMORY SYSTEM

Memory Concepts T:292-295
Semiconductor RAMs T:295-309
ROMs T:309-313
Speed T:313
Size and Cost T:314
Cache Memories T:314-329
Performance Consideration T:329-337
Virtual Memory T:337-343
Memory Management Requirements T:343
Secondary Storage T:344-359

TEXT BOOK
1. T: Carl Hamacher, Zvonko Vranesic and Safwat Zaky, “Computer Organization”, Fifth Edition,Mc Graw-Hill, 2002.

REFERENCES
1. William Stallings, “Computer Organization and Architecture: Designing for Performance”, Sixth Edition, Pearson Education, 2003.
2. David A Patterson and John L.Hennessy, “Computer Organization and Design The hardware / software interface”, Second Edition, Morgan Kaufmann, 2002.
3. John P Hayes, “Computer Architecture and Organization”, Third Edition, McGraw-Hill, 1998.

Unit 1: Basic Structure of Computers

Unit 1: Basic Structure of Computers

Part A:
1. Give an example each of zero address, two address and three address instructions.
2. Which data structure can be best supported using a) indirect addressing mode b) indexed addressing mode?
3. What is a bus? What are the different buses in a CPU?
4. What are the four basic types of operations that need to be supported by an instruction set?
5. Why data bus is bidirectional and address bus is unidirectional in most microprocessor?
6.What are the limitations of assembly language?
7. Define pipeline speedup.
8. What is meant by stored program concept? Discuss.
9. The memory unit of a computer has 256 k words of 32 bits each. The computer has an instruction format with four fields: an operation code field, a mode field to specify one seven addressing modes, a register address field to specify one of 60 processor registers, and a memory address. Specify the instruction format and the number of bits in each field if the instruction is in one memory word.
10. How many 128 X 8 RAM using chips are needed to provide a memory capacity of 2048 bytes?
11. What is the role of PC (program counter) in addressing?
12. How do you determine the instruction execution speed of a processor?
13. Specify the sequence of operation involved when an instruction is executed.
14. Define absolute addressing.
15. What is the different addressing mode?
16. Define index mode.
17. Give example for a)register indirect addressing b)relative addressing
18. What do you mean by interrupt?
19. What is nested interrupt?
20. Define single line bus structure.
21. Define multiple line bus structure.
22. Define CPI.
23. What is register transfer notation? Give examples.
24. What assembly language notations? Give examples.
25. What are stacks and queues?

Part B:
1. Explain in detail the different types of instructions that are supported in a typical processor.
2. Registers R1 and R2 of a computer contain the decimal values 1200 and 2400 respectively. What is the effective address of the memory operand in each of the following instruction?
3. Give the different instruction formats of a CPU in general.
4. Define addressing mode. Classify addressing modes and explain each type with examples.
5. Write an assembly language to find the biggest number among given three numbers.
6. Define instruction set and instruction sequencing.
7. Explain the basic concepts of pipelining and comparing it with sequential processing and draw needed diagrams.
8. What is a stack? Illustrate the use of stack in subroutine processing with suitable diagram.
9. Explain how the performance of the instruction pipeline can be improved.
10. What are the various types of Instruction Set Architectures (ISAs) possible? Discuss.
11. Discuss the various issues to be considered while designing the ISA of a processor.
12. What is a stack? State some uses of the same. Show how a stack can be Implemented using autoincrement and autodecrement addressing modes.
13. Write an assembly language program using the assembly language you are familiar with to add a sequence of n numbers. Give appropriate comments.
14. Draw and explain the block diagram of a simple computer with five functional units.
Describe the different classes of instruction format with example and different addressing modes.
15. How should an instruction format be designed? Discuss the different types of instruction formats bringing out their relative advantages and disadvantages.